Semiconductor packages with an exposed pad or other surfaces for attachment tend to sustain heavy solder voiding levels in the exposed package area during PCB attachment. Such voiding on the pad solder joint can have adverse effects on the thermal performance of the package. In addition, changes to the electrical and thermal path within the completed solder contact can impact certain other applications as well. In certain circumstances, depending on the location of the solder voids, this can result in the completed assembly achieving below desired board performance levels. An example of such a circumstance is when large voids occur directly underneath the position of a semiconductor die. FIG. 1 shows an example of a package assembly indicating 5 areas 100, 102, 104, 106, 108 where there are solder voids which may impact the performance of the package in some respect or another.
There have been a number of proposals of methods to attempt to combat this problem. A commonly accepted industrial practice to overcome these problems has involved putting patterns in a solder paste deposit or patterns of the die attached flag inside the package. U.S. Pat. No. 6,872,661 B1 (leadless plastic chip carrier with etch back pad singulation and a die attached pad array) describes a package which is built from a plurality of single die attached pads and contact pads which attempts to solve some of the problems identified above. However the patent does not resolve these problems for the following reasons:
A die to be mounted is mounted on a plurality of die attached pads which are completely separate from one another. This would provide a relatively low thermal mass in the die attach area.
The described method uses an epoxy material in the die attached process which would not allow this method to be used in power applications.
The patent also discloses a complicated set of steps, including several etch back steps after molding which require special processes during production. This is generally not very efficient or desirable.